Electronic designs for large systems may include millions of gates and megabits of embedded memory. Of the tasks required for managing and optimizing electronic designs on a target device, synthesis, placement, and routing utilizing available resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of computer aided design (CAD) or electronic design automation (EDA) tools to manage and optimize designs. CAD tools perform the time-consuming tasks of synthesis, placement, and routing on a target device.
During synthesis, some CAD tools perform register transfer level (RTL) synthesis which includes optimization of large/coarse design blocks, gate level synthesis which includes the optimization of simpler design blocks such as logic gates, and gate decomposition where large gates are broken down into smaller 2 input gates. Technology mapping is also performed during synthesis where the types of resources available on the target device, such as look up tables (LUTs), are selected to implement the simple 2 input gates of system.
In order to improve the system design, a resynthesis procedure may be performed after synthesis, placement, and/or routing to re-evaluate some synthesis decisions following procedure performed on the system design that may have an impact on delay and area such as clustering or placement. Some resynthesis approaches performed in the past made drastic changes to an existing netlist generated after synthesis which required extensive changes in placement and/or routing. Many of the resynthesis approaches utilized slow analysis methods which were undesirable.